1. Field of the Invention
This invention relates to integrated circuits and, in particular, to packaged integrated circuits in which a lid is attached to a base to enclose a semiconductor die.
2. Related Art
Integrated circuit chips (semiconductor dice on which electrically conductive material is formed) can be packaged in a variety of ways, e.g., encapsulated in plastic, enclosed in ceramic, or enclosed in a metal can, to form packaged integrated circuits. Packaged integrated circuits can be mounted on, for instance, a printed circuit board so that the integrated circuit chip within the package is connected to electrically conductive material outside the package. In through-hole mounting, e.g., dual-in-line packages (DIPs) and pin grid arrays (PGAs), electrically conductive pins that extend outside the package are inserted into holes formed in a mounting board, the holes being coated with electrically conductive material. In surface mounting, e.g., plastic leaded chip carriers (PLCCs) and quad flat packs (QFPs), electrically conductive leads extend outside the package and are attached to electrically conductive material formed on a surface of the mounting board.
FIG. 1A is a cross-sectional view of a prior art cavity-down ceramic pin grid array (PGA) 100. Integrated circuit chip 104 is attached to surface 102a of ceramic base 102 within a cavity formed in base 102. Heat sink 106 is formed in base 102 in proximity to chip 104 such that heat sink 106 is exposed beyond surface 102d of base 102 to the exterior of cavity-down PGA 100. Bond wires 103 are used to make electrical connection between bond pads (not shown) on chip 104 and bond pads (not shown) on surface 102c of base 102. Lid 105 is attached with adhesive 107 to surface 102b of base 102 to seal chip 104 in the cavity. Electrically conductive pins 101 extend from surface 102b of base 102. Pins 101 are electrically connected to the bond pads on surface 102c by electrically conductive vias and traces (not shown) formed in base 102. Cavity-down PGA 100 is mounted on a mounting board by positioning pins 101 in corresponding holes formed in the mounting board, the holes being coated with electrically conductive material.
FIG. 1B is a plan view along direction 1B--1B (FIG. 1A) of cavity-down PGA 100 illustrating surface 102b from which pins 101 extend. For clarity, lid 105, bond wires 103 and heat sink 106 are not shown, and only some of pins 101 are shown. As is evident from FIG. 1B, a large portion of surface 102b from which pins 101 could otherwise extend, is unavailable for that purpose. For instance, pins 101 cannot be located near inner peripheral edge 112a of surface 102b since lid 105 (FIG. 1A) must be attached to surface 102b near edge 112a. Further, a relatively large area (circumscribed by edge 112a in FIG. 1B) must be eliminated from surface 102b in order to allow space for chip 104 and the bond pads on surface 102c.
Given the above constraints, the area defined by outer peripheral edge 112b of surface 102b (the "footprint" of cavity-down PGA 100) must be made large enough so that surface 102b is large enough to accommodate the desired number of pins 101.
FIG. 2 is a cross-sectional view of a prior art cavity-up ceramic PGA 200. Cavity-up PGA 200 is similar to cavity-down PGA 100 and similar elements are designated with the same numerals in FIGS. 1A, 1B and 2. In cavity-up PGA 200, pins 101 extend from surface 102d of base 102, rather than surface 102b of base 102 as in cavity-down PGA 100. In cavity-up PGA 200, the above-noted limitations on usage of surface 102b for placement of pins 101 are not present, since pins 101 do not extend from surface 102b. However, the presence of heat sink 106 still prevents complete usage of surface 102d for pins 101 and the footprint of cavity-up PGA 200 is, like cavity-down PGA 100, undesirably large. While elimination of heat sink 106 would provide more area on surface 102d for pins 101, thereby enabling the footprint of cavity-up PGA 200 to be made smaller, the absence of heat sink 106 would prevent effective removal of heat from cavity-up PGA 200 during operation.
Additionally, in conventional PGAs (either cavity-up or cavity-down), an integrated circuit chip is attached only to a surface, e.g., surface 102a, of the package base, e.g., base 102. The package lid is generally not sufficiently robust to support an integrated circuit chip. Also, the package cavity is not large enough to accommodate a chip attached to the lid and a chip attached to the base.
In a packaged integrated circuit, each integrated circuit chip must be tested for proper functionality after being attached and electrically connected to the package leads. In conventional PGAs, a chip or chips are attached and electrically connected to a package base which also includes a heat sink and the package pins (e.g., FIGS. 1A and 1B). Thus, the chip or chips are tested only after being committed to the relatively expensive package base. If the chip or chips do not perform satisfactorily, the package base must be discarded along with the defective chip or chips.